1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which word lines are grouped into main word lines and sub-word lines such that the main word line is driven by a main decoder circuit and the sub-word line is driven by a divisional decoder circuit in a DRAM (dynamic RAM).
2. Description of Related Art
As shown in FIG. 1, as a large capacity of DRAM is developed, there is proposed a semiconductor memory device in which word lines are grouped into a group of main word lines 12-1 and 12-2 and a group of sub-word lines 13-1 through 13-16 such that the word lines are hierarchized. The main word lines 12-1 and 12-2 are driven by the outputs of main X decoders 14-1 and 14-2, respectively, and the sub-word lines 13-1 through 13-16 are driven by the outputs of divisional decoders 15-1 through 15-16, respectively. The main X decoder 14-1 decodes address signals on row address lines 10-1, 10-3, and 10-4 to drive the main word line 12-1, and the main X decoder 14-2 decodes address signals on row address lines 10-2, 10-3, and 10-4 to drive the main word line 12-2. The divisional decoder 15-1 decodes signals on the main word line 12-1 and a part of remaining row address lines 11-1 to drive the sub-word line 13-1. A divisional decoder 15-2 decodes signals on the main word line 12-1 and a part of remaining row address lines 11-2 to drive the sub-word line 13-2. The other divisional decoder 15-3 through 15-16 decode signals on corresponding word lines and corresponding parts of remaining row address lines in the same manner to drive corresponding sub-word lines, respectively, as shown in the figure.
As examples of the circuit structure of the divisional decoders 15-1 to 15-16, there are proposed three types of circuit structure and these circuit examples are shown in FIGS. 2, 4 and 6, respectively.
First, the circuit shown in FIG. 2 is disclosed in "A boosted Dual Word-line Decoding Scheme for 256 Mb Drams", (Symposium on VLSI circuits Digest of Technical Papers, pp. 112-113, 1992) and is composed of three NMOS transistors 151 to 153. The transistor 151 is a drive transistor for driving the sub-word line SW to the potential of a selected state. The transistor 152 is a reset transistor for resetting the sub-word line SW to the potential of a non-selected state (the ground potential). The transistor 153 is a transfer gate transistor for transferring the potential of a main word line MW to the gate of the drive transistor 151. The gate of this transistor 153 is applied with a fixed potential VB enough to make this transistor 153 always turn on and an address signal RA is supplied to the drain of the transistor 151. Also, the gate of the transistor 152 is applied with a signal having a phase inverse to the main address line MW. Thus, the sub-word line SW is driven by a common connection node of the source of the transistor 151 and the drain of the transistor 152.
FIG. 3 shows examples of signal wave forms of the respective points of the circuit shown in FIG. 2. In a case where the sub-word line SW is to be set to the selected state, the potential of the main word line MW is first set to the H level (high level; the power supply voltage level VB) and at the same time, the potential of the inverse phase signal of a signal on the main word line MW is set to the L level (low level; the ground level) (It is shown in FIG. 3 as the inverted MW and the H level is VCC and VCC&lt;VB is satisfied). Thereafter, the address signal RA is set to the H level so that the sub-word line SW is driven to the H level. As a result, the selected state is achieved. The potential of the gate N2 of the transistor 151 is raised higher than the VB level by the operation of the transfer gate transistor 153 (i.e., it is boosted). Therefore, the source potential of the transistor 151, i.e., the potential of the sub-word line SW is sufficiently driven to the H level.
In a case where the sub-word line SW is to be set to the non-selected state, the potential of the main word line MW is set to the L level and the phase inverted signal is set to the H level.
The circuit shown in FIG. 4 is disclosed in Nikkei Microdevices (November, 1993) and is composed of the two NMOS transistors 255 and 256 and one PMOS transistor 254. The transistor 254 is a drive transistor for driving a sub-word line SW to a selected state. The transistor 256 is a reset transistor for resetting the sub-word line SW to a non-selected state. The transistor 55 is a floating prevention transistor for preventing floating to the sub-word line SW. The gate of the transistor 254 is directly supplied with the potential of the main word line MW and an address signal RA is supplied to the source of the transistor 254. The potential of the main word line MW is supplied to the gate of the transistor 255 and the phase inverted signal (inverted RA) of the address signal RA is supplied to the gate of the transistor 256. The sub-word line SW is connected to the common drain of the transistors 254 to 256.
FIG. 5 shows examples of wave forms of respective portions of the circuit shown in FIG. 4. In a case where the sub-word line SW is to be set to the selected state, the address signal RA is first set to the H level. At the same time, the phase inverted signal (inverted RA) is set to the L level. Further, the potential of the main word line MW is set to the L level.
In a case where the sub-word line SW is to be set to a non-selected state, the address signal RA is set to the L level and the phase inverted signal is set to the H level.
In a case where the sub-word line is to be held in the L level (the non-selected state), the main word line MW is maintained at the H level, thereby the sub-word line SW is maintained at the L level by the transistor 255 which makes it possible to prevent floating.
The circuit shown in FIG. 6 is disclosed in "A 150 MHz 8-Banks 256M Synchronous DRAM with Wave Pipelining Methods" (ISSCC Digest of Technical Papers, pp. 250-251, Feb., 1995) and is composed of three NMOS transistors 357 to 359. The transistor 357 is a transistor for driving a sub-word line SW to a selected state and the transistor 359 is a transistor for transferring an address signal RA to the gate of the transistor 357. The transistor 358 is a transistor for resetting the sub-word line SW to a non-selected state. The main word line MW is connected to the drain of the transistor 357 and the phase inverted signal of the address signal RA is applied to the gate of the transistor 358. The gate of the transistor 359 is applied with a potential VB enough to make this transistor always turn on and the address signal RA is applied to the drain of this transistor. The sub-word line SW is driven by the common connection node of the source of the transistor 357 and the drain of the transistor 358.
FIG. 7 shows examples of wave forms of the respective portion of the circuit shown in FIG. 6. In a case where the sub-word line SW is to be set to the selected state, the main word line MW is first set to the H level and then the address signal RA is set to the H level. At the same time, the phase inverted signal is set to the L level. Upon selection of the sub-word line SW, the potential N3 of the gate of the transistor 357 is raised higher than the VB level by the operation of the transfer gate transistor 359 (i.e., it is boosted). Therefore, the source potential of the transistor 357, i.e. the potential of the sub-word line SW is sufficiently set to the H level.
In a case where the sub-word line SW is to be set to the non-selected state, the address signal RA is set to the L level and the phase inverted signal is set to the H level.
In a case where the sub-word line SW is to be held at the non-selected state, the address signal RA is set to the L level and the phase inverted signal is set to the H level.
In the divisional decoder shown in FIG. 2, the signal having a phase inverse to a signal on the main word line MW, (i.e., an inverted MW) is used. Therefore, there is a problem in that the fault current such as a small leak current between the main word lines MW and the phase inverted signal line, and a short circuit current which is due to the short-circuiting between them can not be relieved.
In the circuit shown in FIG. 4, there is a drawback in that because the CMOS structure which uses the P-type MOS transistors and the N-type MOS transistors is employed, the PN separating area is necessary for the separation between a P-type well and an N-type well on a semiconductor substrate so that the chip area is increased when the circuit is achieved as an IC.
In the circuit shown in FIG. 6, because the structure that the address signal RA is inputted to the gate of the transistor 357 is adopted, the load capacity of the address signal RA becomes large. Therefore, it is necessary to make a drive circuit of the address signal RA large, so that it also causes the increase of the chip area.